Computer Architecture

Instruction set architectures (RISC-V/x86-64), microarchitectural pipelining, cache memory hierarchies, and out-of-order execution engines.

1ISA Foundations & Register Transfer Logic

ALU design, register files, instruction decoding, and RISC-V vs x86-64 execution models.

ISA Foundations & Register Transfer Logic

ALU design, register files, instruction decoding, and RISC-V vs x86-64 execution models.

ISA Foundations & Register Transfer Logic

ALU design, register files, instruction decoding, and RISC-V vs x86-64 execution models.

2Pipelining, Microarchitecture & Hazard Mitigation

5-stage RISC pipelines, structural/data/control hazards, forwarding units, load-use stalls, and dynamic branch prediction.

5-Stage RISC Pipelining, Data Hazards & Forwarding Units

Pipeline registers, hazard detection circuits, data forwarding paths, and 2-bit saturating branch predictors.

5-Stage RISC Pipelines, Forwarding Units & Dynamic Branch Predictors

Master the classic 5-stage RISC execution pipeline, inter-stage pipeline registers, data hazard mitigation via forwarding units, load-use stall insertion, and 2-bit saturating branch prediction state machines.

3Cache Memory Hierarchies & Virtual Memory Systems

Multi-level caches, cache line mapping, write policies, MESI cache coherence protocol, page tables, TLBs, and virtual memory translation.

Multi-Level Caching, MESI Coherence & Translation Lookaside Buffers

Spatial and temporal locality, set associative cache mapping, MESI protocol state machines, and multi-level page table virtual translation.

Multi-Level Cache Hierarchies, MESI Protocol & Two-Level Paging TLB Architecture

Master multi-level memory latency pyramids, N-way set-associative cache line addressing, write-back vs write-through policies, multicore MESI snooping coherence protocols, and two-level page table address translation with Translation Lookaside Buffers.

4Parallel Processors & Out-of-Order Execution

Superscalar architectures, Tomasulo's algorithm, hardware register renaming, Reorder Buffer (ROB), speculative execution, and vector SIMD extensions.

Superscalar Microarchitecture, Register Renaming & Reorder Buffers

Dynamic scheduling, reservation stations, Common Data Bus broadcasts, speculative execution with ROB, and memory disambiguation.

Tomasulo's Algorithm, Register Renaming, Reorder Buffer (ROB) & Memory Disambiguation

Master dynamic out-of-order execution microarchitecture, true vs false register name dependencies, Tomasulo's algorithm with Reservation Stations, the Common Data Bus (CDB), and precise exception recovery via Reorder Buffers.