Hardware Communication Protocols - I2C, SPI & UART

Embedded microcontrollers do not operate in physical isolation; they orchestrate arrays of peripheral integrated circuits—inertial measurement units (IMUs), barometric pressure sensors, flash memory chips, motor drivers, cryptographic coprocessors, and wireless transceivers. The transfer of commands and telemetry between these components relies on low-level hardware communication protocols.

While high-level networks (Ethernet, Wi-Fi, 5G) manage packet routing across global distances, chip-to-chip interconnects must operate within centimeters of PCB trace space under strict physical constraints: minimal pin counts, deterministic microsecond latency, zero software protocol overhead, and direct silicon register accessibility. The three foundational hardware communication pillars of embedded systems are UART (Universal Asynchronous Receiver-Transmitter), SPI (Serial Peripheral Interface), and I2C (Inter-Integrated Circuit).

1. Physical Layer Topologies: Signaling, Duplex Models & Framing#

Physical Serial Signaling Topologies:

UART (Point-to-Point, Asynchronous, Full-Duplex):
[ Microcontroller ] ─── TX Line ───► RX Line ─── [ Peripheral / GPS ]
 ◄─── RX Line ─── TX Line ───

SPI (Master-Slave, Synchronous, Full-Duplex):
[ Master MCU ] ─── SCLK (Clock) ─────────► SCLK ─── [ Slave IMU ]
 ─── MOSI (Data Master Out)─► MOSI
 ◄── MISO (Data Master In) ── MISO
 ─── CS (Chip Select) ─────► CS

I2C (Multi-Master, Synchronous, Half-Duplex, Shared Bus):
+V_DD ──[ R_pullup ]──┐ ┌──[ R_pullup ]──┐
 │ │
[ Master MCU ] ───────┼──┼────────────────┼──────── [ Slave Sensor 1 ]
 SDA (Data) ────────┴──┼────────────────┴──────── SDA
 SCL (Clock) ───────────┴───────────────────────── SCL

Core Communication Dimensions#

1. Synchronous vs. Asynchronous Transmission

• Synchronous Protocols (SPI, I2C):

Include a dedicated physical clock line (SCLK / SCL) driven by the bus master. Data bits are sampled in direct synchronization with clock transitions (rising or falling edges). Transmitter and receiver clocks cannot drift apart, permitting variable transmission speeds and high throughput.

• Asynchronous Protocols (UART):

Operate without a physical clock wire. Transmitter and receiver independently maintain internal hardware baud-rate generators configured to a matching predetermined frequency. Synchronization is re-established dynamically at the start of each frame using electrical edge transitions.

2. Duplex Topologies

• Simplex: Data flows exclusively in one direction (e.g., GPS receiver streaming NMEA strings to an MCU).
• Half-Duplex (I2C, RS-485): Data travels bidirectionally over a shared conductor, but in only one direction at any given microsecond. Devices alternate between transmitting and receiving.
• Full-Duplex (SPI, UART): Simultaneous bidirectional data transmission over independent physical conductors.

2. Universal Asynchronous Receiver-Transmitter (UART)#

UART is an asynchronous, point-to-point hardware transceiver circuit integrated directly into microcontrollers to serialize parallel data words for serial transmission, and vice versa.

UART Standard 8-N-1 Asynchronous Frame Structure:

Voltage
 ▲
High │ IDLE (Mark) │ │ D0 │ D1 │ D2 │ D3 │ D4 │ D5 │ D6 │ D7 │ Optional │ STOP │ IDLE
(Vdd)│─────────────┐ ┌────┬────┬────┬────┬────┬────┬────┬────┐ Parity ┌──────┬─────
 │ │ │ │ │ │ │ │ │ │ │ │ │
Low │ │ START │ │ │ │ │ │ │ │ │ │ │
(GND)│ └────────┴────┴────┴────┴────┴────┴────┴────┴────┴──────────┘ │
─────┴─────────────┴────────┴────────────────────────────────────────┴──────────────┴─────► Time
 |◄-T_bit-►| |◄- 1-2 bits -►|

The UART Frame Architecture#

Because there is no shared clock line, a UART line rests in an electrically HIGH state (Logic 1 / "MARK") when idle. A transmission frame consists of:

1. Start Bit (1 bit): The transmitter pulls the line LOW (Logic 0 / "SPACE") for exactly one bit period (T_bit). This falling edge alerts the receiver's hardware timer to initiate its bit-sampling clock.
2. Data Payload (5 to 9 bits): Standard systems transmit 8 data bits (one byte), clocked Least Significant Bit (LSB) first: D_0 → D_1 → ... → D_7.
3. Optional Parity Bit (1 bit):

- Even Parity: Set to '1' if the count of ones in the data payload is odd, forcing the total count to be even.

- Odd Parity: Set to '1' if the count of ones in the data payload is even.

- None (Standard): Omitted in modern embedded designs in favor of CRC-16 software verification.

1. Stop Bits (1 or 2 bits): The transmitter drives the line HIGH for 1 or 2 bit durations, restoring the line to the idle state and allowing the receiver hardware to rearm for the next falling edge.

The standard embedded configuration is designated 8-N-1 (8 data bits, No parity, 1 stop bit), requiring a total of 1 + 8 + 0 + 1 = 10 bit periods per byte of transmitted payload.

Baud Rate Timing & Sampling Drift Physics#

The baud rate B is the transmission speed in symbols (bits) per second. The duration of each individual bit cell is:

T_bit = (1 / B)

Common standard baud rates include 9,600, 19,200, 38,400, 115,200, and 921,600 bps. At 115,200 bps:

T_bit = (1 / 115,200) ≈ 8.68055 μ s

The 16× Oversampling Receiver Mechanism:

When the receiver detects a falling edge on the RX pin, an internal hardware clock running at 16× the baud rate (f_sample = 16 · B) begins counting.

• The receiver waits 8 ticks (0.5 · T_bit) to confirm the start bit at its exact physical midpoint, rejecting spurious electrical noise spikes.
• Subsequent data bits are sampled every 16 ticks thereafter (1.5 · T_bit, 2.5 · T_bit, ..., 9.5 · T_bit), sampling at the exact mathematical center of each bit window to maximize noise immunity.

Timing Tolerance Limit:

Because the receiver's clock is independent of the transmitter's clock, frequency mismatch causes cumulative sampling point drift. Across a 10-bit frame (Start bit + 8 Data bits + Stop bit), the sampling point must not drift past the boundary of the final bit:

Maximum Accumulated Drift < ± 0.5 · T_bit

Maximum Allowable Clock Frequency Error ≈ (0.5 / 10) = ± 5.0\% (Practically ≤ ± 2.5\% accounting for rise times)

If an internal RC oscillator drifts by more than 3.0\% due to ambient thermal changes, the receiver samples the wrong bit, causing framing errors (FE) and corrupting communications.

3. Serial Peripheral Interface (SPI): Synchronous Streaming#

Developed by Motorola, the Serial Peripheral Interface (SPI) is a high-speed, synchronous, full-duplex, master-slave protocol engineered for streaming data between a host microcontroller and high-bandwidth peripherals (external NOR Flash, graphical LCDs, SD cards, and high-frequency ADCs).

SPI 4-Wire Bus Connection Topology:

Host Microcontroller (Master) Peripheral Device (Slave)
┌───────────────────────────┐ ┌───────────────────────────┐
│ [ SCLK Pin ]├────────────────────►│[ SCLK Pin ] │
│ [ MOSI Pin ]├────────────────────►│[ MOSI Pin ] │
│ [ MISO Pin ]│◄────────────────────┤[ MISO Pin ] │
│ │ │ │
│ [ CS_0 Pin ]├────────────────────►│[ CS / SS Pin ] │
└───────────────────────────┘ └───────────────────────────┘

The 4-Wire Physical Interface#

1. SCLK (Serial Clock): Generated exclusively by the Master. Governs the exact microsecond at which bits are shifted out and latched in. Speeds routinely range from 1 MHz to 80+ MHz.
2. MOSI (Master Out Slave In): Carries data stream from Master to Slave.
3. MISO (Master In Slave Out): Carries data stream from Slave to Master.
4. CS / SS (Chip Select / Slave Select): Active-Low (/CS) pin driven by the Master to address a specific peripheral. When /CS is held LOW (0 V), the slave's MISO output driver is enabled. When HIGH (V_DD), the slave disconnects from the bus, placing its MISO pin into a high-impedance (tri-state / high-Z) floating mode.

The Shift-Register Ring Physics#

At the silicon hardware level, an SPI connection is an 8-bit or 16-bit circular distributed shift register.

SPI Circular Shift-Register Ring Exchange:

Master 8-Bit Shift Register Slave 8-Bit Shift Register
┌───┬───┬───┬───┬───┬───┬───┬───┐ ┌───┬───┬───┬───┬───┬───┬───┬───┐
│b7 │b6 │b5 │b4 │b3 │b2 │b1 │b0 │───[ MOSI ]────►│b7 │b6 │b5 │b4 │b3 │b2 │b1 │b0 │
└───┴───┴───┴───┴───┴───┴───┴───┘ └───┴───┴───┴───┴───┴───┴───┴───┘
 ▲ │
 └────────────────────────[ MISO ]─────────────────┘
On every SCLK pulse:
- Master shifts out b7 to MOSI, shifts in MISO to b0
- Slave shifts out b7 to MISO, shifts in MOSI to b0
Result: After 8 clock cycles, the Master and Slave have swapped bytes completely!

Because every clock pulse simultaneously shifts one bit out and shifts one bit in, SPI is inherently full-duplex. An SPI master cannot read without transmitting; to read a byte from a sensor, the master must write a dummy byte (typically 0xFF or 0x00) to pump the clock.

The Four SPI Modes: Clock Polarity (CPOL) and Clock Phase (CPHA)#

To interface with diverse silicon hardware, SPI establishes four discrete timing configurations defined by two binary parameters:

1. Clock Polarity (CPOL): Defines the idle state of the clock line when no communication is active:

- CPOL = 0: Idle clock is LOW (0 V). Leading edge is Rising, Trailing edge is Falling.

- CPOL = 1: Idle clock is HIGH (V_DD). Leading edge is Falling, Trailing edge is Rising.

1. Clock Phase (CPHA): Defines which clock edge samples the data bit:

- CPHA = 0: Data is sampled on the leading edge of the clock cycle, and shifted on the trailing edge.

- CPHA = 1: Data is shifted on the leading edge, and sampled on the trailing edge.

SPI Clock Modes Matrix:

Mode CPOL CPHA Idle Clock Data Sampled Edge Data Shifted Edge
───────────────────────────────────────────────────────────────────────────────
0 0 0 Low Leading (Rising) Trailing (Falling)
1 0 1 Low Trailing (Falling) Leading (Rising)
2 1 0 High Leading (Falling) Trailing (Rising)
3 1 1 High Trailing (Rising) Leading (Falling)

Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1) are the most widely adopted standards across industrial Flash and sensor ICs.

4. Inter-Integrated Circuit (I2C): Multi-Drop 2-Wire Protocol#

Developed by Philips Semiconductor (now NXP) in 1982, I2C is a synchronous, multi-master, multi-slave, half-duplex serial bus. Where SPI requires a dedicated Chip Select pin for every peripheral (demanding dozens of microcontroller pins), I2C connects dozens of peripherals using exactly two wires.

I2C Open-Drain Bus Architecture with Pull-Up Resistors:

 +3.3V
 │
 ┌────┴────┐
 [ R_p ] [ R_p ] (Pull-up resistors restore lines to HIGH)
 │ │
SDA ──┼─────────┼─────────────────────────── (Serial Data Line)
SCL ──┼─────────┼─────────────────────────── (Serial Clock Line)
 │ │
┌─────┴─────────┴─────┐ ┌─────────────────────┐ ┌─────────────────────┐
│ Master MCU │ │ Slave Sensor (0x48) │ │ Slave EEPROM (0x50) │
│ Open-Drain Drivers │ │ Open-Drain Drivers │ │ Open-Drain Drivers │
└─────────────────────┘ └─────────────────────┘ └─────────────────────┘

1. The Open-Drain Physical Layer & Pull-Up Physics#

The two wires of an I2C bus are:

• SDA (Serial Data): Bidirectional data line.
• SCL (Serial Clock): Clock line driven by the active master.

The Open-Drain / Wired-AND Mechanism:

Unlike standard push-pull output pins (which actively drive pins to both V_DD and GND using complementary P-channel and N-channel MOSFETs), I2C devices utilize Open-Drain outputs:

• A device can pull the line LOW by turning on an internal N-channel MOSFET connected to Ground.
• A device cannot drive the line HIGH. To release the line, it turns off its MOSFET, allowing an external physical pull-up resistor (R_p) to pull the bus voltage back up to V_DD.

Crucial Electrical Safety Advantage:

If two devices transmit conflicting logic states simultaneously (Device A transmits LOW while Device B transmits HIGH), Device A pulls the line to ground, while Device B simply leaves its driver open. The line safely reads LOW. Zero short circuits occur, eliminating silicon burnout during multi-master bus contention.

2. Protocol Framing: START, STOP, Address & ACK/NACK#

Under standard I2C operation, data on the SDA line is allowed to change only when SCL is LOW. SDA must remain stable throughout the entire duration that SCL is HIGH. Violating this rule signifies control conditions:

I2C Framing Signals:

START Condition: STOP Condition:
SCL: ────────┐ SCL: ────────┐
 └────── ┌───────┘
SDA: ────┐ SDA: ┌──────
 └────────── ────────┘
(SDA falls while SCL is HIGH) (SDA rises while SCL is HIGH)

1. START Condition (S): SDA transitions from HIGH to LOW while SCL is held HIGH. Alerts all connected slaves to wake up and listen.
2. 7-Bit Slave Address + Read/Write Bit: The master transmits 8 bits:

- Bits 7-1: The unique 7-bit hardware address of the target peripheral (e.g., 0x48 for a temperature sensor).

- Bit 0 (R//W): Direction flag (0 = Write to slave, 1 = Read from slave).

1. Acknowledge (ACK / NACK): On the 9th clock pulse, the master releases SDA. The targeted slave must pull SDA LOW to assert an ACK (Acknowledge). Leaving SDA HIGH constitutes a NACK (Not-Acknowledge), indicating an unaddressed peripheral or full buffer.
2. Data Payload (8 bits): Transferred sequentially, each followed by an ACK/NACK from the receiving device.
3. STOP Condition (P): SDA transitions from LOW to HIGH while SCL is held HIGH, releasing the bus back to the idle state.

Complete 1-Byte I2C Write Frame:
[ S ] [ 7-Bit Address ] [ W=0 ] [ ACK ] [ 8-Bit Data Byte ] [ ACK ] [ P ]

3. Multi-Master Bitwise Arbitration & Clock Stretching#

1. Bitwise Arbitration:

If two masters initiate transmission simultaneously, both monitor the SDA line while transmitting. Because the bus is a Wired-AND network:

- If Master 1 outputs a '1' (releases SDA) but Master 2 outputs a '0' (pulls SDA low), the physical bus reads '0'.

- Master 1 detects the mismatch between its internal output ('1') and the bus reality ('0').

- Master 1 immediately realizes it has lost arbitration, turns off its SDA driver, and converts into a slave listener without corrupting Master 2's transmission.

1. Clock Stretching:

If an addressed slave is busy processing a complex calculation (e.g., an ADC conversion), it can hold SCL LOW after receiving an ACK. The master detects that SCL is held low and automatically pauses its clock generator until the slave releases SCL, dynamically matching transmission speed to peripheral capability.

5. Architectural Trade-Off Matrix: UART vs. SPI vs. I2C#

6. Industrial Production Implementation: Software Bit-Banging Drivers#

When microcontrollers lack dedicated hardware peripherals or suffer pin-mapping routing conflicts on complex multi-layer PCBs, firmware engineers write Software Bit-Banging Drivers, manually manipulating GPIO output pins and sampling inputs in timing-accurate software loops.

The following production-ready Python module implements:

1. A Software Bit-Banged I2C Master demonstrating START/STOP conditions, 9-bit clocking, and ACK validation.
2. An SPI Mode 0 / Mode 3 Circular Shift Register Engine validating simultaneous full-duplex byte exchanges.

from typing import Tuple, List

# ==========================================================
# 1. SOFTWARE BIT-BANGED I2C MASTER SIMULATOR
# ==========================================================

class BitBangedI2CMaster:
 """Simulates a software bit-banged I2C bus master over open-drain pins."""
 def __init__(self) -> None:
 self.sda: bool = True # Bus lines pulled HIGH by default
 self.scl: bool = True
 self.bus_log: List[str] = []

 def _set_sda(self, state: bool) -> None:
 self.sda = state

 def _set_scl(self, state: bool) -> None:
 self.scl = state

 def start(self) -> None:
 """START Condition: SDA transitions HIGH -> LOW while SCL is HIGH."""
 self._set_sda(True)
 self._set_scl(True)
 self._set_sda(False) # SDA falls
 self._set_scl(False) # SCL falls to prepare data
 self.bus_log.append("SIGNAL: START")

 def stop(self) -> None:
 """STOP Condition: SDA transitions LOW -> HIGH while SCL is HIGH."""
 self._set_sda(False)
 self._set_scl(True)
 self._set_sda(True) # SDA rises
 self.bus_log.append("SIGNAL: STOP")

 def write_byte(self, byte_val: int) -> bool:
 """
 Transmits 8 data bits (MSB first) and clocks 9th bit for Slave ACK.
 Returns True if ACK (SDA=0), False if NACK (SDA=1).
 """
 byte_val &= 0xFF
 for bit_idx in range(7, -1, -1):
 bit = bool((byte_val >> bit_idx) & 1)
 self._set_sda(bit)
 self._set_scl(True) # SCL pulse HIGH (Slave samples bit)
 self._set_scl(False) # SCL falls

 # 9th Clock: Release SDA for Slave ACK
 self._set_sda(True) # Master releases line (pull-up floats HIGH)
 self._set_scl(True) # SCL pulse HIGH
 # Simulated Slave ACK: Target device pulls SDA low
 slave_ack = False # In real hardware: sampled from GPIO IDR
 self._set_scl(False)

 self.bus_log.append(f"WRITE: 0x{byte_val:02X} -> {'ACK' if not slave_ack else 'NACK'}")
 return not slave_ack


# ==========================================================
# 2. SPI FULL-DUPLEX SHIFT REGISTER SIMULATOR
# ==========================================================

class SPIShiftRegisterEngine:
 """Simulates SPI full-duplex circular shift register transfer."""
 def __init__(self, mode: int = 0) -> None:
 # Mode 0: CPOL=0, CPHA=0; Mode 3: CPOL=1, CPHA=1
 if mode not in (0, 3):
 raise ValueError("Supported modes: 0 and 3.")
 self.mode = mode
 self.cpol = 0 if mode == 0 else 1
 self.cpha = 0 if mode == 0 else 1

 def transfer_byte(self, master_out: int, slave_out: int) -> Tuple[int, int]:
 """
 Executes an 8-bit full-duplex SPI clock exchange.
 Returns: (master_in, slave_in)
 """
 master_reg = master_out & 0xFF
 slave_reg = slave_out & 0xFF

 master_in_accum = 0
 slave_in_accum = 0

 # Clock 8 bits (MSB first)
 for _ in range(8):
 # Extract MSBs
 mosi_bit = (master_reg >> 7) & 1
 miso_bit = (slave_reg >> 7) & 1

 # Shift out and shift in
 master_reg = ((master_reg << 1) & 0xFF) | miso_bit
 slave_reg = ((slave_reg << 1) & 0xFF) | mosi_bit

 master_in_accum = (master_in_accum << 1) | miso_bit
 slave_in_accum = (slave_in_accum << 1) | mosi_bit

 return master_in_accum, slave_in_accum


# Verification Execution
if __name__ == "__main__":
 print("=== 1. Testing I2C Bit-Banging Engine ===")
 i2c = BitBangedI2CMaster()
 i2c.start()
 # Write Slave Address 0x48 with Write Bit (0) -> 0x90
 ack1 = i2c.write_byte(0x90)
 # Write Register Address 0x01 (Config Register)
 ack2 = i2c.write_byte(0x01)
 i2c.stop()

 for entry in i2c.bus_log:
 print(f" {entry}")

 print("=== 2. Testing SPI Full-Duplex Byte Swap ===")
 spi = SPIShiftRegisterEngine(mode=0)
 master_tx = 0xA5 # 10100101
 slave_tx = 0x3C # 00111100

 master_rx, slave_rx = spi.transfer_byte(master_tx, slave_tx)
 print(f"Master Transmitted: 0x{master_tx:02X} -> Received: 0x{master_rx:02X}")
 print(f"Slave Transmitted: 0x{slave_tx:02X} -> Received: 0x{slave_rx:02X}")

 assert master_rx == slave_tx, "Master failed to receive slave payload!"
 assert slave_rx == master_tx, "Slave failed to receive master payload!"

7. Common Anti-Patterns & Engineering Pitfalls#

1. I2C Bus Lockup (The Frozen SDA Phenomenon)#

The Anti-Pattern: An MCU resets or crashes in the middle of reading an I2C byte from a slave peripheral.

Why it Breaks: The slave peripheral was in the middle of asserting an ACK or transmitting a data bit '0' when the master reset. The slave holds the SDA line permanently LOW, waiting for the next clock pulse on SCL. When the MCU reboots, it sees SDA held low, assumes another master is using the bus, and hangs forever waiting for the bus to clear.

Correct Practice: Implement an I2C Bus Recovery Routine on boot: configure SCL as a GPIO output, manually toggle SCL for 9 clock cycles to force the slave to finish transmitting its byte, send a STOP condition, and re-initialize the hardware I2C peripheral.

2. Sizing Pull-Up Resistors Naively on I2C#

The Anti-Pattern: Reusing a generic 10 kΩ pull-up resistor across all I2C designs without measuring bus capacitance.

Why it Breaks: PCB traces, connector cables, and peripheral input pins introduce parasitic capacitance (C_bus). The bus rise time is governed by the RC time constant (τ = R_p · C_bus). In Fast Mode (400 kHz), a 10 kΩ pull-up on a high-capacitance bus (200 pF) produces a sluggish rise time (t_r ≈ 0.85 · R_p C_bus = 1,700 ns), far exceeding the maximum allowable 300 ns standard and corrupting communications.

Correct Practice: Calculate pull-up resistance bounds analytically based on bus capacitance and target bus frequency.

3. Floating Chip Select Lines in SPI Multi-Drop Networks#

The Anti-Pattern: Leaving SPI slave Chip Select (/CS) lines floating during MCU boot.

Why it Breaks: During microcontroller reset, all GPIO pins default to high-impedance inputs. Ambient electrical noise pulls multiple /CS pins low simultaneously, causing multiple slave ICs to drive the shared MISO line at the same time, producing electrical bus contention and invalid readings.

Correct Practice: Place external physical 10 kΩ pull-up resistors on all /CS lines to guarantee they remain deasserted (HIGH) during system power-up.

8. Checkpoint Practice Problems#

Problem 1: I2C Pull-Up Resistor Minimum & Maximum Boundary Sizing#

An embedded hardware engineer designs an I2C sensor interface operating in Fast Mode (f_SCL = 400 kHz) on an industrial automation controller board:

• Supply Voltage: V_DD = 3.30 V
• Total measured bus parasitic capacitance (PCB traces + 4 sensor input pins): C_bus = 180 pF
• Microcontroller and sensor maximum open-drain low-level output current: I_OL = 3.0 mA
• Maximum permissible low-level output voltage: V_OL = 0.40 V
• I2C Fast Mode specification mandates a maximum rise time of: t_r, max = 300 ns (3.0 × 10^-7 s)

The maximum rise time for an RC exponential charging curve from 0.3 · V_DD to 0.7 · V_DD is given by:

t_r = 0.8473 · R_p · C_bus

Required:

1. Compute the theoretical minimum pull-up resistance (R_p, min) dictated by maximum sink current I_OL and voltage V_OL.
2. Compute the theoretical maximum pull-up resistance (R_p, max) required to guarantee that line rise time does not exceed 300 ns.
3. State the valid resistance window [R_p, min, R_p, max] and select a standard 5\% tolerance E24 resistor value that optimizes speed and power dissipation.

Step-by-Step Solution:

Step 1: Compute Minimum Pull-Up Resistance (R_p, min)

To protect the open-drain N-channel MOSFET transistors from thermal destruction when pulling the bus LOW, the sink current must not exceed I_OL = 3.0 mA at V_OL = 0.40 V:

R_p, min = (V_DD - V_OL / I_OL) = (3.30 V - 0.40 V / 3.0 × 10^-3 A) = (2.90 V / 0.003 A) ≈ 966.67 Ω

The pull-up resistor must be strictly greater than 967 Ω.

Step 2: Compute Maximum Pull-Up Resistance (R_p, max)

Using the rise time equation with t_r, max = 300 ns and C_bus = 180 pF:

t_r = 0.8473 · R_p · C_bus ≤ 300 × 10^-9 s

R_p, max = (t_r, max / 0.8473 · C_bus) = (300 × 10^-9 / 0.8473 · (180 × 10^-12))

Denominator = 0.8473 × (1.80 × 10^-10) = 1.52514 × 10^-10

R_p, max = (300 × 10^-9 / 1.52514 × 10^-10) ≈ 1,967.03 Ω

The pull-up resistor must be strictly less than 1,967 Ω.

Step 3: State Valid Window and Component Selection

967 Ω ≤ R_p ≤ 1,967 Ω

• A standard E24 resistor value of 1.5 kΩ (1,500 Ω) falls centrally within this window:

- Checking sink current: I = (3.3 - 0.4) / 1,500 = 1.93 mA < 3.0 mA (Safe).

- Checking rise time: t_r = 0.8473 × 1,500 × (180 × 10^-12) ≈ 228.8 ns < 300 ns (Guaranteed timing compliance).

Problem 2: UART Baud Rate Clock Drift & Receiver Sampling Error#

A satellite telemetry modem communicates with an embedded flight computer over an asynchronous UART link configured for 8-N-1 (1 Start bit, 8 Data bits, 1 Stop bit = 10 bits total per frame) at a target baud rate of B = 115,200 bps.

• Ideal bit duration: T_bit = 1 / 115,200 ≈ 8.680556 μ s.
• The receiver detects the start bit falling edge at time t = 0 and samples the final data bit (D_7, the 9th bit in the frame sequence: Start bit is bit 0, D_0 is bit 1, ..., D_7 is bit 8) at its nominal center:

t_sample = (8 + 0.5) · T_bit = 8.5 · T_bit ≈ 73.7847 μ s

• Due to a cheap uncompensated internal RC oscillator operating in freezing temperatures, the transmitter's actual clock runs fast at B_tx = 121,000 bps.

Required:

1. Compute the transmitter's actual bit period (T_bit, tx) and the percentage clock frequency error:

Error = (B_tx - B_nominal / B_nominal) × 100\%

1. Compute the exact physical time interval spanning the start and end of data bit D_7 as generated by the transmitter: [t_start, D7, t_end, D7].
2. Determine whether the receiver's sampling point (t_sample = 73.7847 μ s) falls safely inside the transmitter's D_7 bit window, or if it drifts into the Stop bit, producing a framing error.
3. Calculate the maximum allowable transmitter baud rate before the sampling point slips past the trailing edge of bit D_7.

Step-by-Step Solution:

Step 1: Compute Transmitter Bit Period and Percentage Error

T_bit, tx = (1 / 121,000 bps) ≈ 8.264463 μ s

Clock Error = (121,000 - 115,200 / 115,200) × 100\% = (5,800 / 115,200) × 100\% ≈ +5.0347\%

Step 2: Compute Physical Transmission Window for Bit D_7

Bit D_7 is preceded by 1 Start bit and 7 Data bits (D_0 - D_6) = 8 bits:

• Start of bit D_7:

t_start, D7 = 8 · T_bit, tx = 8 × 8.264463 μ s ≈ 66.1157 μ s

• End of bit D_7:

t_end, D7 = 9 · T_bit, tx = 9 × 8.264463 μ s ≈ 74.3802 μ s

The valid physical window for bit D_7 on the wire is [66.1157 μ s, 74.3802 μ s].

Step 3: Evaluate Sampling Alignment

The receiver samples at:

t_sample = 73.7847 μ s

Check containment:

66.1157 μ s ≤ 73.7847 μ s ≤ 74.3802 μ s

The sampling point falls within the window, but margins are critically razor-thin:

Margin to Trailing Edge = 74.3802 - 73.7847 = 0.5955 μ s

Because 0.5955 μ s is less than 7\% of a bit period, any analog rise-time slope or signal jitter will cause the receiver to sample the subsequent Stop bit, triggering a framing error.

Step 4: Compute Maximum Safe Transmitter Baud Rate

The sampling point t_sample = 73.7847 μ s hits the trailing edge when 9 · T_bit, max = 73.7847 μ s:

T_bit, max = (73.7847 / 9) ≈ 8.1983 μ s

B_max = (1 / 8.1983 × 10^-6) ≈ 121,976 bps

Maximum Percentage Error = (121,976 - 115,200 / 115,200) × 100\% ≈ +5.88\%

At any error beyond +5.88\%, reception fails completely.

Problem 3: SPI vs. I2C Throughput & Protocol Overhead Comparison#

An autonomous drone perception unit reads a 32-byte inertial measurement burst (accelerometer, gyroscope, and magnetometer telemetry) from a sensor chip.

The engineering team compares two bus configurations:

• Design A (4-Wire SPI): Bus clock frequency f_SCLK = 10 MHz. Protocol requires sending a 1-byte read register command, followed immediately by continuous streaming of the 32 data bytes. /CS setup and hold times take a combined 0.5 μ s.
• Design B (I2C Fast Mode): Bus clock frequency f_SCL = 400 kHz. Protocol sequence:

- START condition (1 bit period)

- 7-bit Slave Address + Write Bit + ACK (9 bits)

- 8-bit Register Pointer + ACK (9 bits)

- Repeated START condition (1 bit period)

- 7-bit Slave Address + Read Bit + ACK (9 bits)

- 32 Data Bytes, each with an ACK/NACK bit (32 × 9 = 288 bits)

- STOP condition (1 bit period)

Required:

1. Compute the total number of physical bits transmitted on the wire and the total elapsed transfer time (in microseconds) for Design A (SPI).
2. Compute the total number of physical bits clocked on the bus and the total elapsed transfer time (in microseconds) for Design B (I2C).
3. Calculate the exact speedup factor (Time_I2C / Time_SPI).
4. Compute the protocol efficiency percentage (Payload Bytes / Total Bits Clocked) for both protocols.

Step-by-Step Solution:

Step 1: Compute SPI Transfer Time (Design A)

• Total bytes exchanged = 1 byte (Command) + 32 bytes (Data) = 33 bytes.
• Total bits = 33 × 8 = 264 bits.
• Clock frequency f = 10 MHz ⇒ T_bit = 1 / (10 × 10^6) = 0.1 μ s.

Clocking Time = 264 × 0.1 μ s = 26.4 μ s

Total Elapsed Time = Clocking Time + T_CS = 26.4 μ s + 0.5 μ s = 26.9 μ s

Step 2: Compute I2C Transfer Time (Design B)

Summing all bit events:

• START = 1 bit
• Device Address (Write) + ACK = 9 bits
• Register Address + ACK = 9 bits
• Repeated START = 1 bit
• Device Address (Read) + ACK = 9 bits
• 32 Data Bytes with ACKs = 32 × 9 = 288 bits
• STOP = 1 bit

Total Bits Clocked = 1 + 9 + 9 + 1 + 9 + 288 + 1 = 318 bits

Clock frequency f = 400 kHz ⇒ T_bit = 1 / (400 × 10^3) = 2.50 μ s.

Total Elapsed Time = 318 bits × 2.50 μ s/bit = 795.0 μ s

Step 3: Speedup Factor

Speedup = (Time_I2C / Time_SPI) = (795.0 μ s / 26.9 μ s) ≈ 29.55 ×

SPI executes the telemetry acquisition almost 30× faster than I2C Fast Mode.

Step 4: Protocol Efficiency Analysis

Useful payload = 32 bytes = 256 bits.

• SPI Efficiency:

Efficiency_SPI = (256 bits / 264 bits) × 100\% = 96.97\%

• I2C Efficiency:

Efficiency_I2C = (256 bits / 318 bits) × 100\% = 80.50\%

SPI provides both higher raw clock frequencies and superior transmission efficiency by eliminating in-band address headers and ACK clock pulses.

Problem 4: I2C Multi-Master Bus Arbitration Race#

Two microcontroller bus masters (M_1 and M_2) connected to the same I2C bus initiate transmission at the exact same microsecond:

• M_1 attempts to write to slave address 0x4C (binary: 1001100, followed by Write bit 0).
• M_2 attempts to write to slave address 0x48 (binary: 1001000, followed by Write bit 0).

Recall that I2C operates as a Wired-AND bus:

• A master outputting '0' drives the bus to 0 V (dominant bit).
• A master outputting '1' releases the bus to 3.3 V (recessive bit).
• If a master outputs '1' but samples '0' on the bus, it immediately loses arbitration and ceases transmission.

Required:

1. Write out the full 8-bit address byte stream (7-bit address + Write bit 0) for M_1 and M_2.
2. Step through each bit transmission from Bit 7 (MSB) to Bit 0:

- Identify the output of M_1.

- Identify the output of M_2.

- State the resulting physical voltage state of the SDA bus.

- Determine whether both masters remain in contention.

1. Identify the exact bit position where arbitration is decided, state which master wins arbitration, and explain why the winning master's transmission proceeds without corruption.

Step-by-Step Solution:

Step 1: Construct 8-Bit Address Streams

• Master 1: Address 0x4C = 1001100. Append Write bit '0':

Stream_1 = [1, 0, 0, 1, 1, 1, 0, 0] (Wait: 0x4C in binary is 01001100_2?)

Let's verify standard 7-bit addressing representation:

0x4C in 7-bit binary is:

4 = 0100_2, C = 1100_2 → 7-bit value is 1001100_2 (64 + 8 + 4 = 76_10 = 0x4C).

Shifted left by 1 with Write bit 0:

Byte_1 = (0x4C << 1) | 0 = 0x98 = 10011000_2

Bit sequence (MSB to LSB):

- Bit 7: 1

- Bit 6: 0

- Bit 5: 0

- Bit 4: 1

- Bit 3: 1

- Bit 2: 0

- Bit 1: 0

- Bit 0: 0

• Master 2: Address 0x48 = 1001000 (64 + 8 = 72_10 = 0x48).

Shifted left by 1 with Write bit 0:

Byte_2 = (0x48 << 1) | 0 = 0x90 = 10010000_2

Bit sequence (MSB to LSB):

- Bit 7: 1

- Bit 6: 0

- Bit 5: 0

- Bit 4: 1

- Bit 3: 0

- Bit 2: 0

- Bit 1: 0

- Bit 0: 0

Step 2: Bit-by-Bit Arbitration Tracing

• Bit 7:

- M_1 outputs '1', M_2 outputs '1'.

- Bus State = 1 ∧ 1 = 1. Both see '1'. Contention continues.

• Bit 6:

- M_1 outputs '0', M_2 outputs '0'.

- Bus State = 0 ∧ 0 = 0. Both see '0'. Contention continues.

• Bit 5:

- M_1 outputs '0', M_2 outputs '0'.

- Bus State = 0 ∧ 0 = 0. Both see '0'. Contention continues.

• Bit 4:

- M_1 outputs '1', M_2 outputs '1'.

- Bus State = 1 ∧ 1 = 1. Both see '1'. Contention continues.

• Bit 3:

- M_1 outputs '1' (releases SDA).

- M_2 outputs '0' (pulls SDA to Ground).

- Physical Bus State = 1 ∧ 0 = 0.

- M_2 intended '0' and observes '0' (Continues unhindered).

- M_1 intended '1' but observes '0'!

- Arbitration is decided at Bit 3!

Step 3: Conclusion & Seamless Operation

• M_1 detects that another device has asserted '0'. M_1 immediately disables its SDA output driver and switches to slave/idle mode.
• Master 2 wins arbitration.
• Because M_2 held the line LOW at Bit 3, M_1's release caused zero electrical perturbation on the bus. Master 2's transmission proceeds with 100\% integrity, completely unaware that contention even occurred.